| 2025 | ISCAS | A 4-Phase Adaptive On-Time Controlled Buck Converter With Auto-Synchronized Dynamic Frequency and Transient-Enhancement Techniques. | Zhiming He, Sai-Weng Sin, Rui Paulo Martins, Yan Lu |
| 2024 | ISCAS | A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation. | Ran Zhang, Ka-Fai Un, Mingqiang Guo, Liang Qi, Dengke Xu, Weibing Zhao, Rui Paulo Martins, Franco Maloberti, Sai-Weng Sin |
| 2022 | ISCAS | A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC. | Ke Li, Sai-Weng Sin, Liang Qi, Weibing Zhao, Guoxing Wang, Rui Paulo Martins |
| 2021 | ISCAS | Discrete-Time MASH Delta-Sigma Modulator with Second-Order Digital Noise Coupling for Wideband High-Resolution Applications. | Xinyu Qin, Jingying Zhang, Liang Qi, Sai-Weng Sin, Rui Paulo Martins, Guoxing Wang |
| 2018 | IECON | A Power Quality Indexes Measurement System Platform with Remote Alarm Notification. | Jianyang Deng, Chi-Seng Lam, Man-Chung Wong, Lei Wang, Sai-Weng Sin, Rui Paulo Martins |
| 2018 | ISCAS | Design and Control of An Integrated 3-Level Boost Converter under DCM Operation. | Yiwei Tan, Chi-Seng Lam, Sai-Weng Sin, Man-Chung Wong, Rui Paulo Martins |
| 2017 | IECON | CCM operation analysis and parameters design of Negative Output Elementary Luo Converter for ripple suppression. | Chi-Wa U, Chi-Seng Lam, Man-Kay Law, Sai-Weng Sin, Man-Chung Wong, Seng-Pan U, Rui Paulo Martins |
| 2014 | ISCAS | Jitter-resistant Capacitor Based Sine-Shaped DAC for Continuous-Time Sigma-Delta modulators. | Da Feng, Franco Maloberti, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins |
| 2013 | ISCAS | A continuous-time VCO-assisted VCO-based ΣΔ modulator with 76.6dB SNDR and 10MHz BW. | Yun Du, Tao He, Yang Jiang, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins |
| 2013 | ISCAS | A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS. | Wen-Lan Wu, Yan Zhu, Li Ding, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins |
| 2012 | ISCAS | A 10MHz BW 78dB DR CT ΣΔ modulator with novel switched high linearity VCO-based quantizer. | Tao He, Yang Jiang, Yun Du, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins |
| 2010 | ISCAS | A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs. | Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins |
| 2008 | ISCAS | A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier. | He Gong Wei, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins |
| 2006 | ISCAS | A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications. | Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins |
| 2006 | ISCAS | A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits. | Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins |
| 2005 | ISCAS | A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuits. | Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins |
| 2005 | ISCAS | A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits. | Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins |
| 2004 | ISCAS | A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems. | Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins |
| 2003 | ICASSP | Quantitative noise analysis of jitter-induced nonuniformly sampled-and-held signals. | Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins |
| 2003 | ISCAS | Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output. | Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Jos E. Franca |