Satyanand Nalam
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
5
Active years
2008–2014
Best venue rank
A*
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2014 | VLSID | Pipelined Non-strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories. | Sudhanshu Khanna, Satyanand Nalam, Benton H. Calhoun |
| 2011 | DATE | Dynamic write limited minimum operating voltage for nanoscale SRAMs. | Satyanand Nalam, Vikas Chandra, Robert C. Aitken, Benton H. Calhoun |
| 2010 | DAC | Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers. | Satyanand Nalam, Mudit Bhargava, Ken Mai, Benton H. Calhoun |
| 2009 | ICCD | A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes. | Satyanand Nalam, Mudit Bhargava, Kyle Ringgenberg, Ken Mai, Benton H. Calhoun |
| 2008 | ISLPED | Analyzing static and dynamic write margin for nanometer SRAMs. | Jiajing Wang, Satyanand Nalam, Benton H. Calhoun |