| 2024 | VLSID | Optimal Placement of TDC Sensor for Enhanced Power Side-Channel Assessment on FPGAS. | Debayan Das, Majid Sabbagh, Rana Elnaggar, Guang Chen, Sayak Ray, Jason M. Fung |
| 2023 | DAC | Power Side-Channel Vulnerability Assessment of Lightweight Cryptographic Scheme, XOODYAK. | Anupam Golder, Debayan Das, Santosh Ghosh, Avinash Varna, Majid Sabbagh, Sayak Ray, Rana Elnaggar, Joseph Friel, Daniel Dinu, Jason M. Fung |
| 2023 | ICCAD | Secure-by-Construction Design Methodology for CPUs: Implementing Secure Speculation on the RTL. | Tobias Jauch, Alex Wezel, Mohammad Rahmani Fadiheh, Philipp Schmitz, Sayak Ray, Jason M. Fung, Christopher W. Fletcher, Dominik Stoffel, Wolfgang Kunz |
| 2022 | DAC | Automating hardware security property generation: invited. | Ryan Kastner, Francesco Restuccia, Andres Meza, Sayak Ray, Jason M. Fung, Cynthia Sturton |
| 2019 | DAC | Formal Verification of Security Critical Hardware-Firmware Interactions in Commercial SoCs. | Sayak Ray, Nishant Ghosh, Ramya Jayaram Masti, Arun K. Kanuparthi, Jason M. Fung |
| 2019 | FMCAD | Verification of Authenticated Firmware Loaders. | Sujit Kumar Muduli, Pramod Subramanyan, Sayak Ray |
| 2018 | DAC | Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware. | Bo-Yuan Huang, Sayak Ray, Aarti Gupta, Jason M. Fung, Sharad Malik |
| 2017 | DATE | Malware detection using machine learning based analysis of virtual memory access patterns. | Zhixing Xu, Sayak Ray, Pramod Subramanyan, Sharad Malik |
| 2015 | ASPDAC | BEE: Predicting realistic worst case and stochastic eye diagrams by accounting for correlated bitstreams and coding strategies. | Aadithya V. Karthik, Sayak Ray, Jaijeet Roychowdhury |
| 2015 | FMCAD | Template-based Synthesis of Instruction-Level Abstractions for SoC Verification. | Pramod Subramanyan, Yakir Vizel, Sayak Ray, Sharad Malik |
| 2014 | ASPDAC | ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification. | Aadithya V. Karthik, Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury |
| 2013 | MEMOCODE | Ranking structure in communication fabrics. | Sayak Ray, Robert K. Brayton |
| 2012 | DATE | Scalable progress verification in credit-based flow-control systems. | Sayak Ray, Robert K. Brayton |
| 2012 | DATE | Mapping into LUT structures. | Sayak Ray, Alan Mishchenko, Niklas En, Robert K. Brayton, Stephen Jang, Chao Chen |
| 2011 | FMCAD | Enhancing ABC for stabilization verification of SystemVerilog/VHDL models. | Jiang Long, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton |
| 2008 | ATVA | A Dynamic Assertion-Based Verification Platform for Validation of UML Designs. | Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, Partha Pratim Chakrabarti, S. Ramesh, P. Vignesh V. Ganesan |
| 2007 | VLSID | A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis. | Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti |