| 2026 | ASPDAC | ML-driven Design Technology Co-Optimization Framework for Advanced Technology Nodes. | Hyunbae Seo, Handong Cho, Sehyeon Chung, Kyu-Myung Choi, Taewhan Kim |
| 2026 | ASPDAC | Enhancing Pin Accessibility Through Pin Pattern Migration and Optimization Across Cell Boundaries. | Hyunbae Seo, Sehyeon Chung, Taewhan Kim |
| 2025 | DAC | Late Breaking Results: Utilization of Hybrid Threshold-Voltage Flip-flops for Power Recovery. | Sehyeon Chung, Hyun-chul Hwang, Byung-Su Kim, Jaeha Lee, Kunhyuk Kang, Taewhan Kim |
| 2025 | ICCAD | Adaptive Pin Pattern Modification on Standard Cells Towards ECO Routing. | Jaehoon Ahn, Sehyeon Chung, Taewhan Kim |
| 2025 | ICCAD | Synthesis of Standard Cells of Minimum Delay. | Sehyeon Chung, Hyunbae Seo, Taewhan Kim |
| 2025 | ICCD | Timing-Driven Multi-Bit Flip-Flop Allocation Utilizing Design-Technology Co-Optimization Techniques. | Yeongyeong Shin, Sehyeon Chung, Taewhan Kim |
| 2024 | DATE | Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes. | Handong Cho, Hyunbae Seo, Sehyeon Chung, Kyu-Myung Choi, Taewhan Kim |
| 2024 | ICCAD | Optimal Layout Synthesis of Multi-Row Standard Cells for Advanced Technology Nodes. | Sehyeon Chung, Hyunbae Seo, Handong Cho, Kyumyung Choi, Taewhan Kim |
| 2023 | DATE | Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility. | Jooyeon Jeong, Sehyeon Chung, Kyeongrok Jo, Taewhan Kim |
| 2022 | ISLPED | Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis. | Sehyeon Chung, Jooyeon Jeong, Taewhan Kim |
| 2022 | ISLPED | Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs. | Suwan Kim, Sehyeon Chung, Taewhan Kim, Heechun Park |