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Seokin Hong

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

31

Venues

9

Active years

2010–2026

Best venue rank

A*

Where they publish

Papers

31 indexed papers, newest first.

YearVenueTitleAuthors
2026DATEScrooge: Accelerating Attention Inference in LLMs via Early Termination Mechanism.Gwangeun Byeon, Seongwook Kim, Taein Kim, Jungmin Lee, Seokin Hong
2026DATEBraid-ZNS: Leveraging Zone Random Write Area for Efficient In-Storage Compression on ZNS SSDs.Minkyu Choi, Joonseong Hwang, Minjin Park, Seokin Hong
2026DATELupin: Spatial Resource Stealing with Outlier-First Encoding for Mixed-Precision LLM Acceleration.Taein Kim, Sukhyun Han, Seongwook Kim, Gwangeun Byeon, Jungmin Lee, Seokin Hong
2026DATEBoosting LLC Bandwidth Utilization in GPUs through Adaptive Fine-Grained Data Migration.Jihun Yoon, Sungbin Jang, Seokin Hong
2025DACPIMPAL: Accelerating LLM Inference on Edge Devices via In-DRAM Arithmetic Lookup.Yoonho Jang, Hyeongjun Cho, Yesin Ryu, Jungrae Kim, Seokin Hong
2025DATEZebra: Leveraging Diagonal Attention Pattern for Vision Transformer Accelerator.Sukhyun Han, Seongwook Kim, Gwangeun Byeon, Jihun Yoon, Seokin Hong
2025DATEImproving Address Translation in Tagless DRAM Cache by Caching PTE Pages.Osang Kwon, Yongho Lee, Seokin Hong
2025DATEBuddy ECC: Making Cache Mostly Clean in CXL-Based Memory Systems for Enhanced Error Correction at Low Cost.Yongho Lee, Junbum Park, Osang Kwon, Sungbin Jang, Seokin Hong
2025DATESPB: Towards Low-Latency CXL Memory via Speculative Protocol Bypassing.Junbum Park, Yongho Lee, Sungbin Jang, Wonyoung Lee, Seokin Hong
2025ICCDMinimizing Read Disturb via Localized Page Allocation for Modern NAND Flash-Based SSDs.Joonseong Hwang, Minkyu Choi, Minjin Park, Jihun Yoon, Yoonho Jang, Seokin Hong
2025ICCDDDLM: Demand-Aware Dynamic Link Width Management for Energy-Efficient CXL Memory.Taejeong Kim, Junbum Park, Yongho Lee, Seokin Hong
2025ISCAAvalanche: Optimizing Cache Utilization via Matrix Reordering for Sparse Matrix Multiplication Accelerator.Gwangeun Byeon, Seongwook Kim, Hyungjin Kim, Sukhyun Han, Jinkwon Kim, Prashant J. Nair, Taewook Kang, Seokin Hong
2025MICROLeveraging Chiplet-Locality for Efficient Memory Mapping in Multi-Chip Module GPUs.Junhyeok Park, Sungbin Jang, Osang Kwon, Yongho Lee, Seokin Hong
2025MICROSoftWalker: Supporting Software Page Table Walk for Irregular GPU Applications.Sungbin Jang, Junhyeok Park, Yongho Lee, Osang Kwon, Donghyun Kim, Juyoung Seok, Seokin Hong
2024MICRODistributed Page Table: Harnessing Physical Memory as an Unbounded Hashed Page Table.Osang Kwon, Yongho Lee, Junhyeok Park, Sungbin Jang, Byungchul Tak, Seokin Hong
2024MICROA Case for Speculative Address Translation with Rapid Validation for GPUs.Junhyeok Park, Osang Kwon, Yongho Lee, Seongwook Kim, Gwangeun Byeon, Jihun Yoon, Prashant J. Nair, Seokin Hong
2023ACMLFacto-CNN: Memory-Efficient CNN Training with Low-rank Tensor Factorization and Lossy Tensor Compression.Seungtae Lee, Jonghwan Ko, Seokin Hong
2023ICCDConveyor: Towards Asynchronous Dataflow in Systolic Array to Exploit Unstructured Sparsity.Seongwook Kim, Gwangeun Byeon, Sihyung Kim, Hyungjin Kim, Seokin Hong
2022DACDon't open row: rethinking row buffer policy for improving performance of non-volatile memories.Yongho Lee, Osang Kwon, Seokin Hong
2020ICCDADAM: Adaptive Block Placement with Metadata Embedding for Hybrid Caches.Beomjun Kim, Prashant J. Nair, Seokin Hong
2019ASPLOSSplit-CNN: Splitting Window-based Operations in Convolutional Neural Networks for Memory System Optimization.Tian Jin, Seokin Hong
2019MICROTouch: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads.Seokin Hong, Blent Abali, Alper Buyuktosunoglu, Michael B. Healy, Prashant J. Nair
2018MICROAttach: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads.Seokin Hong, Prashant Jayaprakash Nair, Blent Abali, Alper Buyuktosunoglu, Kyu-Hyoun Kim, Michael B. Healy
2017HPCAPartial Row Activation for Low-Power DRAM System.Yebin Lee, Hyeonggyu Kim, Seokin Hong, Soontae Kim
2014ICCDTernary cache: Three-valued MLC STT-RAM caches.Seokin Hong, Jongmin Lee, Soontae Kim
2013DATEAVICA: an access-time variation insensitive L1 cache architecture.Seokin Hong, Soontae Kim
2013HPCASkinflint DRAM system: Minimizing DRAM chip writes for low power.Yebin Lee, Soontae Kim, Seokin Hong, Jongmin Lee
2013HPCAMacho: A failure model-oriented adaptive cache architecture to enable near-threshold voltage scaling.Tayyeb Mahmood, Soontae Kim, Seokin Hong
2011ISLPEDTLB index-based tagging for cache energy reduction.Jongmin Lee, Seokin Hong, Soontae Kim
2011MICROResidue cache: a low-energy low-area L2 cache architecture via compression and partial hits.Soontae Kim, Jongmin Lee, Jesung Kim, Seokin Hong
2010ICCDLizard: Energy-efficient hard fault detection, diagnosis and isolation in the ALU.Seokin Hong, Soontae Kim