Seongil O
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
9
Venues
5
Active years
2013–2021
Best venue rank
A*
Where they publish
Papers
9 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2021 | ISCA | Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product. | Sukhan Lee, Shinhaeng Kang, Jaehoon Lee, Hyeonsu Kim, Eojin Lee, Seungwoo Seo, Hosang Yoon, Seungwon Lee, Kyounghwan Lim, Hyunsung Shin, Jinhyun Kim, Seongil O, Anand Iyer, David Wang, Kyomin Sohn, Nam Sung Kim |
| 2017 | HPCA | Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices. | Sang-uhn Cha, Seongil O, Hyunsung Shin, Sangjoon Hwang, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi, Gyo-Young Jin, Young Hoon Son, Hyunyoon Cho, Jung Ho Ahn, Nam Sung Kim |
| 2015 | HPCA | CiDRA: A cache-inspired DRAM resilience architecture. | Young Hoon Son, Sukhan Lee, Seongil O, Sanghyuk Kwon, Nam Sung Kim, Jung Ho Ahn |
| 2015 | ISCA | Architecting to achieve a billion requests per second throughput on a single key-value store server platform. | Sheng Li, Hyeontaek Lim, Victor W. Lee, Jung Ho Ahn, Anuj Kalia, Michael Kaminsky, David G. Andersen, Seongil O, Sukhan Lee, Pradeep Dubey |
| 2015 | ICS | History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures. | Ke Chen, Sheng Li, Jung Ho Ahn, Naveen Muralimanohar, Jishen Zhao, Cong Xu, Seongil O, Yuan Xie, Jay B. Brockman, Norman P. Jouppi |
| 2014 | ISCA | Row-buffer decoupling: A case for low-latency DRAM microarchitecture. | Seongil O, Young Hoon Son, Nam Sung Kim, Jung Ho Ahn |
| 2014 | SC | Microbank: Architecting Through-Silicon Interposer-Based Main Memory Systems. | Young Hoon Son, Seongil O, Hyunggyun Yang, Daejin Jung, Jung Ho Ahn, John Kim, Jangwoo Kim, Jae W. Lee |
| 2013 | ISCA | Reducing memory access latency with asymmetric DRAM bank organizations. | Young Hoon Son, Seongil O, Yuhwan Ro, Jae W. Lee, Jung Ho Ahn |
| 2013 | ISPASS | McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling. | Jung Ho Ahn, Sheng Li, Seongil O, Norman P. Jouppi |