Sergei Y. Larin
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
1996–1999
Best venue rank
A*
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1999 | MICRO | Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors. | Sergei Y. Larin, Thomas M. Conte |
| 1998 | ASPLOS | Value Speculation Scheduling for High Performance Processors. | Chao-ying Fu, Matthew D. Jennings, Sergei Y. Larin, Thomas M. Conte |
| 1996 | MICRO | Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. | Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye |