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Sergey Tverdyshev

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

12

Venues

11

Active years

2007–2023

Best venue rank

A

Where they publish

Papers

12 indexed papers, newest first.

YearVenueTitleAuthors
2023RTCSARDMA-Based Deterministic Communication Architecture for Autonomous Driving.Hazem Abaza, Abhinaba Habishyashi, Debayan Roy, Andrea Bastoni, Zain Alabedin Haj Hammadeh, Shiqing Fan, Selma Saidi, Sergey Tverdyshev
2022DSDMonitoring Framework to Support Mixed-Criticality Applications on Multicore Platforms.Gautam Gala, Carlos Rodriguez, Veaceslav Monaco, Javier Castillo, Gerhard Fohler, Veaceslav Falico, Sergey Tverdyshev
2022MODELSWARDA Model-based System Engineering Plugin for Safety Architecture Pattern Synthesis.Yuri Gil Dantas, Tiziano Munaro, Carmen Crlan, Vivek Nigam, Simon Barner, Shiqing Fan, Alexander Pretschner, Ulrich Schpp, Sergey Tverdyshev
2020DSNTowards Host Intrusion Detection for Embedded Industrial Systems.Marine Kadar, Sergey Tverdyshev, Gerhard Fohler
2019ECRTSSystem Calls Instrumentation for Intrusion Detection in Embedded Mixed-Criticality Systems.Marine Kadar, Sergey Tverdyshev, Gerhard Fohler
2015CRITISSecurity Architecture and Specification Framework for Safe and Secure Industrial Automation.Sergey Tverdyshev, Holger Blasum, Ekaterina Rudina, Dmitry Kulagin, Pavel Dyakin, Stanislav Moiseev
2012DSNMILS-related information flow control in the avionic domain: A view on security-enhancing software architectures.Kevin Mueller, Michael Paulitsch, Sergey Tverdyshev, Holger Blasum
2011ISORCProving Memory Separation in a Microkernel by Code Level Verification.Christoph Baumann, Thorsten Bormer, Holger Blasum, Sergey Tverdyshev
2009CSRFormal Verification of Gate-Level Computer Systems.Mark A. Hillebrand, Sergey Tverdyshev
2009FMCADA verified platform for a gate-level electronic control unit.Sergey Tverdyshev
2008TIMEEfficient Bit-Level Model Reductions for Automated Hardware Verification.Sergey Tverdyshev, Eyad Alkassar
2007CADEFormal Device and Programming Model for a Serial Interface.Eyad Alkassar, Mark A. Hillebrand, Steffen Knapp, Rostislav Rusev, Sergey Tverdyshev