| 2026 | ISCAS | InFP: A 17.97 TFLOPS/W Reconfigurable SRAM Based Computing-in-Memory Macro for BF16 MAC Operations. | Jing Zhang, Tianchu Dong, Shaoxuan Li, Zhengxi Yan, Shanshi Huang |
| 2025 | ASPDAC | MICSim: A Modular Simulator for Mixed-signal Compute-in-Memory based AI Accelerator. | Cong Wang, Zeming Chen, Shanshi Huang |
| 2025 | DAC | An Efficient Compute-in-Memory based Accelerator for Point-based Point Cloud Neural Networks. | Xipeng Lin, Cong Wang, Shanshi Huang, Hongwu Jiang |
| 2025 | DATE | OpenC | Tianchu Dong, Shaoxuan Li, Yihang Zuo, Hongwu Jiang, Yuzhe Ma, Shanshi Huang |
| 2024 | ICCAD | Voxel-CIM: An Efficient Compute-in-Memory Accelerator for Voxel-based Point Cloud Neural Networks. | Xipeng Lin, Shanshi Huang, Hongwu Jiang |
| 2021 | DATE | A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator. | Anni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu |
| 2021 | ISCAS | Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning. | Shanshi Huang, Xiaochen Peng, Hongwu Jiang, Yandong Luo, Shimeng Yu |
| 2020 | DAC | A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training. | Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Jian-Wei Su, Yen-Chi Chou, Wei-Hsing Huang, Ta-Wei Liu, Ruhui Liu, Meng-Fan Chang, Shimeng Yu |
| 2020 | DATE | Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories. | Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu |
| 2020 | ICCAD | XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption. | Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu |
| 2020 | ISCAS | MINT: Mixed-Precision RRAM-Based IN-Memory Training Architecture. | Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Shimeng Yu |