Shigeru Takasaki
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
3
Active years
1981–1990
Best venue rank
A*
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1990 | ICCD | HAL III: function level hardware logic simulation. | Shigeru Takasaki, Nobuyoshi Nomizu, Yoshihiro Hirabayashi, Hiroshi Ishikura, Masahiro Kurashita, Nobuhiko Koike, Toshiyuki Nakata |
| 1986 | DAC | HAL II: a mixed level hardware logic simulation system. | Shigeru Takasaki, Tohru Sasaki, Nobuyoshi Nomizu, Hiroshi Ishikura, Nobuhiko Koike |
| 1981 | ITC | A Calculus of Testability Measure at the Functional Level. | Shigeru Takasaki, Masato Kawai, Shigehiro Funatsu, Akihiko Yamada |