| 2017 | ICCAD | Overview of the 2017 CAD contest at ICCAD: Invited paper. | Myung-Chul Kim, Shih-Hsu Huang, Rung-Bin Lin, Shigetoshi Nakatake |
| 2016 | ICCAD | Overview of the 2016 CAD contest at ICCAD. | Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim, Shigetoshi Nakatake |
| 2015 | ISCAS | Subblock-level matching layout for analog block-pair and its manufacturability evaluation. | Takuya Hirata, Ryuta Nishino, Shigetoshi Nakatake, Masaya Shimoyama, Masashi Miyagawa, Koichi Tanno, Akihiro Yamada |
| 2012 | ISCAS | A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model. | Gong Chen, Bo Yang, Shigetoshi Nakatake, Zhangcai Huang, Yasuaki Inoue |
| 2010 | ASPDAC | D-A converter based variation analysis for analog layout design. | Bo Liu, Toru Fujimura, Bo Yang, Shigetoshi Nakatake |
| 2010 | ASPDAC | Regularity-oriented analog placement with diffusion sharing and well island generation. | Shigetoshi Nakatake, Masahiro Kawakita, Takao Ito, Masahiro Kojima, Michiko Kojima, Kenji Izumi, Tadayuki Habasaki |
| 2010 | ICCAD | Structured analog circuit design and MOS transistor decomposition for high accuracy applications. | Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake |
| 2010 | ISCAS | Post-placement STI well width adjusting by geometric programming for device mobility enhancement in critical path. | Jing Li, Bo Yang, Qing Dong, Shigetoshi Nakatake |
| 2008 | ASPDAC | Constraint-free analog placement with topological symmetry structure. | Qing Dong, Shigetoshi Nakatake |
| 2008 | ISCAS | Transistor-level programmable MOS analog IC with body biasing. | Toru Fujimura, Shigetoshi Nakatake |
| 2007 | ASPDAC | Structured Placement with Topological Regularity Evaluation. | Shigetoshi Nakatake |
| 2004 | ASPDAC | Abstraction and optimization of consistent floorplanning with pillar block constraints. | Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani |
| 2004 | ASPDAC | Multi-level placement with circuit schema based clustering in analog IC layouts. | Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani |
| 2004 | ISCAS | A fast algorithm for crosspoint assignment under crosstalk constraints with shielding effects. | Keiji Kida, Xiaoke Zhu, Changwen Zhuang, Yasuhiro Takashima, Shigetoshi Nakatake |
| 2002 | VLSID | Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. | Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita |
| 2000 | ASPDAC | Self-reforming routing for stochastic search in VLSI interconnection layout. | Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani |
| 2000 | VLSID | Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. | Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake |
| 1998 | ASPDAC | Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules. | Shigetoshi Nakatake, Masahiro Furuya, Yoji Kajitani |
| 1998 | ICCAD | The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. | Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita |
| 1998 | ICCAD | The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks. | Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani |
| 1996 | ICCAD | Module placement on BSG-structure and IC layout applications. | Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani |
| 1995 | ICCAD | Rectangle-packing-based module placement. | Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani |
| 1994 | ICCAD | Channel-driven global routing with consistent placement (extended abstract). | Shigetoshi Nakatake, Yoji Kajitani |