| 2021 | DAC | Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks. | Sai Kiran Cherupally, Adnan Siraj Rakin, Shihui Yin, Mingoo Seok, Deliang Fan, Jae-sun Seo |
| 2021 | DATE | Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design. | Jyotishman Saikia, Shihui Yin, Sai Kiran Cherupally, Bo Zhang, Jian Meng, Mingoo Seok, Jae-Sun Seo |
| 2020 | DATE | An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays. | Shruti R. Kulkarni, Shihui Yin, Jae-sun Seo, Bipin Rajendran |
| 2020 | ICCAD | FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory. | Shreyas K. Venkataramanaiah, Han-Sok Suh, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-Sun Seo |
| 2020 | IJCAI | Efficient and Modularized Training on FPGA for Real-time Applications. | Shreyas Kolala Venkataramanaiah, Xiaocong Du, Zheng Li, Shihui Yin, Yu Cao, Jae-sun Seo |
| 2019 | ACSSC | Vesti: An In-Memory Computing Processor for Deep Neural Networks Acceleration. | Zhewei Jiang, Shihui Yin, Minkyu Kim, Tushar Gupta, Mingoo Seok, Jae-sun Seo |
| 2019 | FPL | Automatic Compiler Based FPGA Accelerator for CNN Training. | Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo |
| 2019 | ICASSP | Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks. | Gaurav Srivastava, Deepak Kadetotad, Shihui Yin, Visar Berisha, Chaitali Chakrabarti, Jae-sun Seo |
| 2019 | ISCAS | ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression. | Sai Kiran Cherupally, Gaurav Srivastava, Shihui Yin, Deepak Kadetotad, Chisung Bae, Sang Joon Kim, Jae-sun Seo |
| 2019 | ISLPED | K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM. | Jyotishman Saikia, Shihui Yin, Zhewei Jiang, Mingoo Seok, Jae-sun Seo |
| 2018 | DATE | XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks. | Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, Shimeng Yu |
| 2017 | ACSSC | Minimizing area and energy of deep learning hardware design using collective low precision and structured compression. | Shihui Yin, Gaurav Srivastava, Shreyas K. Venkataramanaiah, Chaitali Chakrabarti, Visar Berisha, Jae-sun Seo |
| 2017 | ICCAD | Efficient programming of reconfigurable radio frequency (RF) systems. | Mohamed Baker Alawieh, Fa Wang, Jun Tao, Shihui Yin, Minhee Jun, Xin Li, Tamal Mukherjee, Rohit Negi |
| 2016 | ASPDAC | Re-thinking polynomial optimization: Efficient programming of reconfigurable radio frequency (RF) systems by convexification. | Fa Wang, Shihui Yin, Minhee Jun, Xin Li, Tamal Mukherjee, Rohit Negi, Larry T. Pileggi |
| 2015 | ASPDAC | Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data. | Ying-Chih Wang, Shihui Yin, Minhee Jun, Xin Li, Lawrence T. Pileggi, Tamal Mukherjee, Rohit Negi |
| 2015 | GLOBECOM | Phase Noise Impairment and Environment-Adaptable Fast (EAF) Optimization for Programming of Reconfigurable Radio Frequency (RF) Receivers. | Minhee Jun, Rohit Negi, Shihui Yin, Fa Wang, Megha Sunny, Tamal Mukherjee, Xin Li |