| 2024 | Tencon | Stixu: An Open-Source Idea for Planning Integrated Circuit Layouts Efficiently. | Nicholas Overacker, James Stine, Michal Ptaszynski, Shingo Yoshizawa, Miho Kobayashi |
| 2017 | VTC | Interleaved Domain Interference Canceller for Low Latency IDMA System and Its VLSI Implementation. | Tran Thi Thao Nguyen, Leonardo Lanante, Yuhei Nagao, Masayuki Kurosaki, Shingo Yoshizawa, Hiroshi Ochi |
| 2013 | PIMRC | Effectiveness of cover and reflector in receiver antennas for MIMO line-of-sight channels. | Shingo Yoshizawa, Masahiro Sugitani, Yoshikazu Miyanaga |
| 2012 | ISCAS | A low-power MMSE MIMO detector using dynamic voltage wordlength scaling for 44 MIMO-OFDM systems. | Jaeseong Kim, Shingo Yoshizawa, Yoshikazu Miyanaga |
| 2011 | ISCAS | An area and power efficient pipeline FFT processor for 88 MIMO-OFDM systems. | Shingo Yoshizawa, Atsushi Orikasa, Yoshikazu Miyanaga |
| 2010 | ISCAS | Scalable pipeline architecture of MMSE MIMO detector for 44 MIMO-OFDM receiver. | Shingo Yoshizawa, Hirokazu Ikeuchi, Yoshikazu Miyanaga |
| 2010 | PIMRC | Development and outdoor evaluation of an experimental platform in an 80-MHz bandwidth 22 MIMO-OFDM system at 5.2-GHz band. | Shingo Yoshizawa, Shinya Odagiri, Yasuhiro Asai, Takashi Gunji, Takashi Saito, Yoshikazu Miyanaga |
| 2009 | ISCAS | VLSI Implementation of a 44 MIMO-OFDM transceiver with an 80-MHz Channel Bandwidth. | Shingo Yoshizawa, Yoshikazu Miyanaga |
| 2008 | ISCAS | Reconfigurable two-dimensional pipeline FFT processor in OFDM cognitive radio systems. | Shingo Yoshizawa, Kazuto Nishi, Yoshikazu Miyanaga |
| 2008 | ISCAS | A complete pipelined MMSE detection architecture in a 4x4 MIMO-OFDM receiver. | Shingo Yoshizawa, Yasushi Yamauchi, Yoshikazu Miyanaga |
| 2007 | ISCAS | Dynamic Reconfigurable Architecture for a Low-Power Despreader in VSF-OFCDM Systems. | Takayuki Sugawara, Shingo Yoshizawa, Yoshikazu Miyanaga |
| 2007 | ISCAS | Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation. | Shingo Yoshizawa, Yoshikazu Miyanaga |
| 2006 | ISCAS | Direct control on modulation spectrum for noise-robust speech recognition and spectral subtraction. | Naoya Wada, Noboru Hayasaka, Shingo Yoshizawa, Yoshikazu Miyanaga |
| 2006 | ISCAS | Tunable word length architecture for low power wireless OFDM demodulator. | Shingo Yoshizawa, Yoshikazu Miyanaga |
| 2006 | ISCAS | 300-Mbps OFDM baseband transceiver for wireless LAN systems. | Shingo Yoshizawa, Yoshikazu Miyanaga, Hiroshi Ochi, Yoshio Itoh, Nobuo Hataoka, Baiko Sai, Norihisa Takayama, Masaki Hirata |
| 2005 | ISCAS | Robust VLSI architecture for system-on-chip design and its implementation in Viterbi decoder. | Yasuyuki Hatakawa, Shingo Yoshizawa, Yoshikazu Miyanaga |
| 2004 | ICASSP | Cepstral gain normalization for noise robust speech recognition. | Shingo Yoshizawa, Noboru Hayasaka, Naoya Wada, Yoshikazu Miyanaga |
| 2004 | ISCAS | Scalable architecture for word HMM-based speech recognition. | Shingo Yoshizawa, Naoya Wada, Noboru Hayasaka, Yoshikazu Miyanaga |