Shinobu Fujita
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
12
Venues
7
Active years
2006–2015
Best venue rank
A*
Where they publish
Papers
12 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2015 | ICCD | Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches. | Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura |
| 2014 | ASPDAC | Novel nonvolatile memory hierarchies to realize "normally-off mobile processors". | Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe |
| 2013 | DATE | D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. | Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura |
| 2010 | DAC | Detachable nano-carbon chip with ultra low power. | Shinobu Fujita, Shinichi Yasuda, Daesung Lee, Xiangyu Chen, Deji Akinwande, H.-S. Philip Wong |
| 2010 | FPGA | High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only). | Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita |
| 2010 | ISCAS | Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies. | Kumiko Nomura, Keiko Abe, Shinobu Fujita, Yasuhiko Kurosawa, Atsushi Kageshima |
| 2009 | DATE | Nano-electronics challenge chip designers meet real nano-electronics in 2010s? | Shinobu Fujita |
| 2009 | FPGA | CMOS vs Nano: comrades or rivals? | Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, Andr DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger |
| 2009 | ISCAS | Perspectives and Issues in 3D-IC from Designers' Point of View. | Shinobu Fujita, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Tetsufumi Tanamoto |
| 2008 | ICCAD | A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. | Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini |
| 2008 | ISCAS | ROM based logic (RBL) design: High-performance and low-power adders. | Bipul Chandra Paul, Shinobu Fujita, Masaki Okajima |
| 2006 | DAC | Modeling and analysis of circuit performance of ballistic CNFET. | Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee |