| 2012 | SSBSE | Testing of Concurrent Programs Using Genetic Algorithms. | Vendula Hrub, Bohuslav Krena, Zdenek Letko, Shmuel Ur, Toms Vojnar |
| 2011 | ICSE | Code coverage analysis in practice for large systems. | Yoram Adler, Noam Behar, Orna Raz, Onn Shehory, Nadav Steindler, Shmuel Ur, Aviad Zlotnick |
| 2011 | SSBSE | Highly Scalable Multi Objective Test Suite Minimisation Using Graphics Cards. | Shin Yoo, Mark Harman, Shmuel Ur |
| 2010 | ICSE | Combinatorial test design in practice. | Myra B. Cohen, Shmuel Ur |
| 2010 | ICSE | Improving throughput via slowdowns. | Maayan Goldstein, Onn Shehory, Rachel Tzoref-Brill, Shmuel Ur |
| 2010 | ISSTA | A platform for search-based testing of concurrent software. | Bohuslav Krena, Zdenek Letko, Toms Vojnar, Shmuel Ur |
| 2009 | ICSE | Automated substring hole analysis. | Yoram Adler, Eitan Farchi, Moshe Klausner, Dan Pelleg, Orna Raz, Moran Shochat, Shmuel Ur, Aviad Zlotnick |
| 2009 | ICST | Measuring and Improving Latency to Avoid Test Suite Wear Out. | Shin Yoo, Mark Harman, Shmuel Ur |
| 2009 | ISSTA | Advanced code coverage analysis using substring holes. | Yoram Adler, Eitan Farchi, Moshe Klausner, Dan Pelleg, Orna Raz, Moran Shochat, Shmuel Ur, Aviad Zlotnick |
| 2009 | ISSTA | Forcing small models of conditions on program interleaving for detection of concurrent bugs. | Ehud Trainin, Yarden Nir-Buchbinder, Rachel Tzoref-Brill, Aviad Zlotnick, Shmuel Ur, Eitan Farchi |
| 2009 | RV | A Concurrency Testing Tool and Its Plug-Ins for Dynamic Analysis and Runtime Healing. | Bohuslav Krena, Zdenek Letko, Yarden Nir-Buchbinder, Rachel Tzoref-Brill, Shmuel Ur, Toms Vojnar |
| 2008 | EuroPar | Topic 1: Support Tools and Environments. | Marios D. Dikaiakos, Omer F. Rana, Shmuel Ur, Joo Loureno |
| 2008 | ICST | Experience with a Concurrency Bugs Benchmark. | Yaniv Eytani, Rachel Tzoref, Shmuel Ur |
| 2008 | ICST | Selective Homeworkless Reviews. | Eitan Farchi, Shmuel Ur |
| 2008 | ISSTA | 6th workshop on parallel and distributed systems: testing and debugging (PADTAD '08). | Shmuel Ur, Scott D. Stoller, Eitan Farchi |
| 2008 | RV | Deadlocks: From Exhibiting to Healing. | Yarden Nir-Buchbinder, Rachel Tzoref, Shmuel Ur |
| 2007 | ISSTA | Healing data races on-the-fly. | Bohuslav Krena, Zdenek Letko, Rachel Tzoref, Shmuel Ur, Toms Vojnar |
| 2007 | ISSTA | Instrumenting where it hurts: an automatic concurrent debugging technique. | Rachel Tzoref, Shmuel Ur, Elad Yom-Tov |
| 2006 | ISoLA | Noise Makers Need to Know Where to be Silent - Producing Schedules That Find Bugs. | Yosi Ben-Asher, Eitan Farchi, Yaniv Eytani, Shmuel Ur |
| 2006 | ISSTA | Producing scheduling that causes concurrent programs to fail. | Yosi Ben-Asher, Yaniv Eytani, Eitan Farchi, Shmuel Ur |
| 2005 | EuroPar | Multi-threaded Testing with AOP Is Easy, and It Finds Bugs!. | Shady Copty, Shmuel Ur |
| 2005 | PPoPP | Applications of synchronization coverage. | Arkady Bron, Eitan Farchi, Yonit Magid, Yarden Nir, Shmuel Ur |
| 2004 | DAC | Probabilistic regression suites for functional verification. | Shai Fine, Shmuel Ur, Avi Ziv |
| 2004 | ISoLA | Probabilistic Alternative Regression Suites. | Shady Copty, Shai Fine, Shmuel Ur, Avi Ziv |
| 2002 | DAC | Hole analysis for functional coverage data. | Oded Lachish, Eitan Marcus, Shmuel Ur, Avi Ziv |
| 2002 | FM | Improvements in Coverability Analysis. | Gil Ratsaby, Baruch Sterin, Shmuel Ur |
| 2001 | ITC | Cost evaluation of coverage directed test generation for the IBM mainframe. | Gilly Nativ, Steven Mittermaier, Shmuel Ur, Avi Ziv |
| 1999 | DAC | Micro Architecture Coverage Directed Generation of Test Programs. | Shmuel Ur, Yaov Yadin |
| 1998 | DAC | User Defined Coverage - A Tool Supported Methodology for Design Verification. | Raanan Grinwald, Eran Harel, Michael Orgad, Shmuel Ur, Avi Ziv |
| 1997 | APSEC | Compacting regression-suites on-the-fly. | Erez Buchnik, Shmuel Ur |
| 1996 | FMCAD | Coverage-Directed Test Generation Using Symbolic Techniques. | Daniel Geist, Monica Farkas, Avner Landver, Yossi Lichtenstein, Shmuel Ur, Yaron Wolfsthal |
| 1996 | FMCAD | A Methodology for Processor Implementation Verification. | Daniel Lewin, Dean H. Lorenz, Shmuel Ur |