Shogo Nakaya
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
3
Active years
1996–2001
Best venue rank
A*
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2001 | FPL | Arithmetic Operation Oriented Reconfigurable Chip: RHW. | Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara |
| 2000 | FCCM | Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW. | Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara |
| 1998 | AAAI | Evolvable Hardware Chip for High Precision Printer Image Compression. | Hidenori Sakanashi, Mehrdad Salami, Masaya Iwata, Shogo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Tetsuya Higuchi |
| 1996 | FCCM | SOP: a reconfigurable massively parallel system and its control-data-flow based compiling method. | Tsukasa Yamauchi, Shogo Nakaya, Nobuki Kajihara |