Shounak Dhar
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
4
Active years
2016–2019
Best venue rank
A*
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | ASPDAC | A shape-driven spreading algorithm using linear programming for global placement. | Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan |
| 2019 | DAC | DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement. | Yibo Lin, Shounak Dhar, Wuxi Li, Haoxing Ren, Brucek Khailany, David Z. Pan |
| 2019 | FPL | FPGA Accelerated FPGA Placement. | Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan |
| 2018 | ASPDAC | Logic synthesis for energy-efficient photonic integrated circuits. | Zheng Zhao, Zheng Wang, Zhoufeng Ying, Shounak Dhar, Ray T. Chen, David Z. Pan |
| 2016 | ICCAD | Detailed placement for modern FPGAs using 2D dynamic programming. | Shounak Dhar, Saurabh N. Adya, Love Singhal, Mahesh A. Iyer, David Z. Pan |
| 2016 | ICCAD | UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packing. | Wuxi Li, Shounak Dhar, David Z. Pan |