Shu-Yu Jiang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
1
Active years
2003–2006
Best venue rank
C
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2006 | ISCAS | Self-sampled vernier delay line for built-in clock jitter measurement. | Kuo-Hsing Cheng, Chan-Wei Huang, Shu-Yu Jiang |
| 2005 | ISCAS | A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. | Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang |
| 2004 | ISCAS | Static divided word matching line for low-power Content Addressable Memory design. | Kuo-Hsing Cheng, Chia-Hung Wei, Shu-Yu Jiang |
| 2003 | ISCAS | BIST for clock jitter measurements. | Kuo-Hsing Cheng, Shu-Yu Jiang, Zong-Shen Chen |