| 2023 | ASPDAC | BufFormer: A Generative ML Framework for Scalable Buffering. | Rongjian Liang, Siddhartha Nath, Anand Rajaram, Jiang Hu, Haoxing Ren |
| 2022 | DAC | Generative self-supervised learning for gate sizing: invited. | Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Haoxing Ren |
| 2022 | ICCAD | TransSizer: A Novel Transformer-Based Fast Gate Sizer. | Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Haoxing Ren |
| 2022 | ICCAD | Why are Graph Neural Networks Effective for EDA Problems?: (Invited Paper). | Haoxing Ren, Siddhartha Nath, Yanqing Zhang, Hao Chen, Mingjie Liu |
| 2021 | DAC | RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning. | Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim |
| 2021 | ICCAD | Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning. | Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim |
| 2021 | ICCAD | Optimizing VLSI Implementation with Reinforcement Learning - ICCAD Special Session Paper. | Haoxing Ren, Saad Godil, Brucek Khailany, Robert Kirby, Haiguang Liao, Siddhartha Nath, Jonathan Raiman, Rajarshi Roy |
| 2020 | ICCAD | A Fast Learning-Driven Signoff Power Optimization Framework. | Yi-Chen Lu, Siddhartha Nath, Sai Surya Kiran Pentapati, Sung Kyu Lim |
| 2016 | ASPDAC | Learning-based prediction of embedded memory timing failures during initial floorplan design. | Wei-Ting Jonas Chan, Kun Young Chung, Andrew B. Kahng, Nancy D. MacDonald, Siddhartha Nath |
| 2016 | ICCD | BEOL stack-aware routability prediction from placement using data mining techniques. | Wei-Ting Jonas Chan, Yang Du, Andrew B. Kahng, Siddhartha Nath, Kambiz Samadi |
| 2015 | DAC | 3DIC benefit estimation and implementation guidance from 2DIC implementation. | Wei-Ting Jonas Chan, Siddhartha Nath, Andrew B. Kahng, Yang Du, Kambiz Samadi |
| 2015 | DAC | A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction. | Kwangsoo Han, Jiajia Li, Andrew B. Kahng, Siddhartha Nath, Jongpil Lee |
| 2015 | ICCAD | Toward Metrics of Design Automation Research Impact. | Andrew B. Kahng, Mulong Luo, Gi-Joon Nam, Siddhartha Nath, David Z. Pan, Gabriel Robins |
| 2014 | DATE | A deep learning methodology to proliferate golden signoff timing. | Seung-Soo Han, Andrew B. Kahng, Siddhartha Nath, Ashok S. Vydyanathan |
| 2014 | ICCD | ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap. | Juan Antonio Carballo, Wei-Ting Jonas Chan, Paolo A. Gargini, Andrew B. Kahng, Siddhartha Nath |
| 2014 | ICCD | The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap. | Wei-Ting Jonas Chan, Andrew B. Kahng, Siddhartha Nath, Ichiro Yamamoto |
| 2013 | ASPDAC | Optimization of overdrive signoff. | Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath |
| 2013 | ASPDAC | On potential design impacts of electromigration awareness. | Andrew B. Kahng, Siddhartha Nath, Tajana Rosing |
| 2013 | DATE | Enhanced metamodeling techniques for high-dimensional IC design estimation problems. | Andrew B. Kahng, Bill Lin, Siddhartha Nath |
| 2013 | ICCAD | Incremental multiple-scan chain ordering for ECO flip-flop insertion. | Andrew B. Kahng, Ilgweon Kang, Siddhartha Nath |
| 2012 | DAC | Explicit modeling of control and data for improved NoC router estimation. | Andrew B. Kahng, Bill Lin, Siddhartha Nath |