| 2021 | ISCAS | A Computational Efficient Architecture for Extremely Sparse Stereo Network. | Tan Huang, Sih-Sian Wu, Jan Klopp, Po-Hsiang Yu, Liang-Gee Chen |
| 2021 | ISCAS | Online Training Refinement Network and Architecture Design for Stereo Matching. | Yu-Sheng Wu, Sih-Sian Wu, Tan Huang, Liang-Gee Chen |
| 2018 | ISCAS | Accurate and Bandwidth Efficient Architecture for CNN-based Full-HD Super-Resolution. | Chung-Yan Chih, Sih-Sian Wu, Jan P. Klopp, Liang-Gee Chen |
| 2017 | MMSP | Accurate and fast segment-based cost aggregation algorithm for stereo matching. | Da-Fang Chang, Sih-Sian Wu, Hsin-Yu Hou, Liang-Gee Chen |
| 2015 | ISCAS | Memory efficient architecture for belief propagation based disparity estimation. | Sih-Sian Wu, Hong-Hui Chen, Chen-Han Tsai, Liang-Gee Chen |
| 2014 | DATE | A thermal resilient integration of many-core microprocessors and main memory by 2.5D TSI I/Os. | Sih-Sian Wu, Kanwen Wang, Sai Manoj Pudukotai Dinakarrao, Tsung-Yi Ho, Mingbin Yu, Hao Yu |
| 2010 | DAC | New model-driven design and generation of multi-facet arbiters part I: from the design model to the architecture model. | Jer-Min Jou, Sih-Sian Wu, Yun-Lung Lee, Cheng Chou, Yuan-Long Jeang |