Sithara Raveendran
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
3
Active years
2016–2022
Best venue rank
C
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2022 | ISCAS | On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic. | Sithara Raveendran, Pranose J. Edavoor, Y. B. Nithin Kumar, M. H. Vasantha |
| 2018 | Tencon | Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter. | Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha |
| 2016 | VLSID | Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell. | A. Venkatareddy, Sithara Raveendran, Kumar Y. B. Nithin, M. H. Vasantha |