| 2015 | ISCAS | Fault-aware configurable logic block for reliable reconfigurable FPGAs. | B. Chagun Basha, Sbastien Pillement, Stanislaw J. Piestrak |
| 2014 | DSD | Design of Fault-Secure Transposed FIR Filters Protected Using Residue Codes. | Stanislaw J. Piestrak, Piotr Patronik |
| 2013 | DSD | Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs. | Syed M. A. H. Jafri, Stanislaw J. Piestrak, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen |
| 2011 | DDECS | Error recovery technique for coarse-grained reconfigurable architectures. | Muhammad Moazam Azeem, Stanislaw J. Piestrak, Olivier Sentieys, Sbastien Pillement |
| 2011 | ISCAS | Design of multi-residue generators using shared logic. | Stanislaw J. Piestrak |
| 2011 | ISLPED | Fast and energy-efficient constant-coefficient FIR filters using residue number system. | Piotr Patronik, Krzysztof S. Berezowski, Stanislaw J. Piestrak, Janusz Biernat, Aviral Shrivastava |
| 2010 | DSD | On Reducing Error Rate of Data Protected Using Systematic Unordered Codes in Asymmetric Channels. | Stanislaw J. Piestrak |
| 2010 | ISCAS | Design of cost-efficient multipliers modulo 2 | Stanislaw J. Piestrak |
| 2009 | CASES | Exploiting residue number system for power-efficient digital signal processing in embedded processors. | Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shrivastava, Stanislaw J. Piestrak |
| 2007 | IOLTS | Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes. | Fabrice Monteiro, Stanislaw J. Piestrak, Houssein Jaber, Abbas Dandache |
| 2006 | IOLTS | Characterizing Laser-Induced Pulses in ICs: Methodology and Results. | Damien Leroy, Stanislaw J. Piestrak, Fabrice Monteiro, Abbas Dandache, Stphane Rossignol, Pascal Moitrel |
| 2005 | IOLTS | Modeling of Transients Caused by a Laser Attack on Smart Cards. | Damien Leroy, Stanislaw J. Piestrak, Fabrice Monteiro, Abbas Dandache |
| 2001 | IOLTS | On the Design of Self-Testing Checkers for Modified Berger Codes. | Stanislaw J. Piestrak, Dimitris Bakalis, Xrysovalantis Kavousianos |
| 1999 | EDCC | Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits. | Jerzy W. Greblicki, Stanislaw J. Piestrak |
| 1994 | ICCD | Design of TSC Code-Disjoint Inverter-Free PLA's for Separable Unordered Codes. | Stanislaw J. Piestrak |
| 1994 | ICCD | Design of High-Speed Residue-to-Binary Number System Converter Based on Chinese Remainder Theorem. | Stanislaw J. Piestrak |
| 1991 | ARITH | Design of residue generators and multioperand modular adders using carry-save adders. | Stanislaw J. Piestrak |
| 1991 | ICCD | Design of a Self-Testing Checker for Borden Code. | Stanislaw J. Piestrak |