| 2025 | ASPDAC | SMART-GPO: Gate-Level Sensitivity Measurement with Accurate Estimation for Glitch Power Optimization. | Yikang Ouyang, Yuchao Wu, Dongsheng Zuo, Subhendu Roy, Tinghuan Chen, Zhiyao Xie, Yuzhe Ma |
| 2017 | ISLPED | A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders. | Subhendu Roy, Yuzhe Ma, Jin Miao, Bei Yu |
| 2016 | ICCAD | LRR-DPUF: learning resilient and reliable digital physical unclonable function. | Jin Miao, Meng Li, Subhendu Roy, Bei Yu |
| 2015 | ASPDAC | Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs. | Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan |
| 2015 | DAC | OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions. | Subhendu Roy, Derong Liu, Junhyung Um, David Z. Pan |
| 2015 | ICCD | CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction. | Chen-Hsuan Lin, Subhendu Roy, Chun-Yao Wang, David Z. Pan, Deming Chen |
| 2014 | VLSID | Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown. | Subhendu Roy, David Z. Pan |
| 2013 | DAC | Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures. | Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan |