Sung-En Hsieh
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
2015–2016
Best venue rank
C
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2016 | ISCAS | A 0.3V 0.705fJ/conversion-step 10-bit SAR ADC with shifted monotonie switching scheme in 90nm CMOS. | Sung-En Hsieh, Chih-Cheng Hsieh |
| 2015 | ISCAS | A 1.2V 1MS/s 7.65fJ/conversion-step 12-bit hybrid SAR ADC with time-to-digital converter. | Sung-En Hsieh, Cheng-Kang Ho, Chih-Cheng Hsieh |