Syed Ershad Ahmed
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
2011–2016
Best venue rank
National
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2016 | ARITH | An Iterative Logarithmic Multiplier with Improved Precision. | Syed Ershad Ahmed, Sanket Kadam, M. B. Srinivas |
| 2016 | VLSID | A Hybrid Energy Efficient Digital Comparator. | Syed Ershad Ahmed, S. Sweekruth Srinivas, M. B. Srinivas |
| 2014 | VLSID | A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter. | Ch. Santosh Varma, Syed Ershad Ahmed, M. B. Srinivas |
| 2012 | VLSID | Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. | Chetan Kumar Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas |
| 2011 | DSD | A Unified Architecture for BCD and Binary Adder/Subtractor. | Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas |