Tadayoshi Horita
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
2
Active years
2000–2012
Best venue rank
National
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2012 | PRDC | A Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays by Direct Spare Replacement. | Itsuo Takanami, Tadayoshi Horita |
| 2009 | PDPTA | A Computer Cluster for Tests of Parallel Programming Environments Including Operating Systems. | Tadayoshi Horita, Koichi Kitano, Koji Teramoto |
| 2009 | PDPTA | An Implementation of a Fault-Tolerant 2D Systolic Array on FPGAs and Its Evaluation. | Tadayoshi Horita, Itsuo Takanami |
| 2009 | PDPTA | Novel Value Injection Learning Methods Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant. | Kazuhiro Nishimura, Tadayoshi Horita, Masato Otsu, Itsuo Takanami |
| 2001 | PRDC | Analytical Results for Reconfiguration of E-11/2- Track Switch Torus Arrays with Multiple Fault Types. | Tadayoshi Horita, Itsuo Takanami |
| 2000 | PDPTA | A System for Efficiently Self-Reconstructing 1½-Track Switch Torus Arrays. | Tadayoshi Horita, Itsuo Takanami |