| 2026 | ISCAS | Implementation and Evaluation of a Cryogenic DSP in 22-nm with Floating-Point Arithmetic for Estimating Qubit States. | Yuki Koyama, Takashi Imagawa, Ryo Kishida, Takefumi Miyoshi, Kazutoshi Kobayashi |
| 2024 | QCE | A Power Reduction Scheme by Arithmetic Format Conversion for a DSP to Estimate Qubit States Under 4K Cryogenic Environment. | Takashi Imagawa, Ryo Kishida, Yuki Koyama, Kazutoshi Kobayashi, Takefumi Miyoshi |
| 2021 | DATE | MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA. | Takashi Imagawa, Jaehoon Yu, Masanori Hashimoto, Hiroyuki Ochi |
| 2015 | ASPDAC | Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. | Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera |
| 2013 | DATE | A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis. | Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato |
| 2009 | FPL | Coarse-grained dynamically reconfigurable architecture with flexible reliability. | Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye |