Takeo Kakuda
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
1990–1990
Best venue rank
A
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1990 | ICCAD | Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams. | Masahiro Fujita, Yusuke Matsunaga, Takeo Kakuda |
| 1990 | ICCAD | Multi-Level Logic Minimization Across Latch Boundaries. | Yusuke Matsunaga, Masahiro Fujita, Takeo Kakuda |