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Teerachot Siriburanon

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

12

Venues

2

Active years

2013–2025

Best venue rank

B

Where they publish

Papers

12 indexed papers, newest first.

YearVenueTitleAuthors
2025ISCASTrifilar-Transformer-Coupled Series-Resonance Oscillator with Enhanced Tuning Range.Sumit Dash, Sayan Kumar, Teerachot Siriburanon, Robert Bogdan Staszewski
2025ISCASA Ring Temperature Sensor for Quantum Applications.Ali Esmailiyan, Eugene Koskin, Dennis Andrade-Miceli, Andrii Sokolov, Teerachot Siriburanon, Dirk Leipold, David J. Redmond, Imran Bashir, Elena Blokhina, Robert Bogdan Staszewski
2025ISCASA 0.012mmAli Esmailiyan, Teerachot Siriburanon, Dennis Andrade-Miceli, Eugene Koskin, Dirk Leipold, David J. Redmond, Imran Bashir, Elena Blokhina, Robert Bogdan Staszewski
2025ISCASA 4kb 4T eDRAM with Balanced Retention Time Adjustment.Sayan Kumar, Dennis Andrade-Miceli, Chawin Khongprasongsiri, Teerachot Siriburanon, Robert Bogdan Staszewski
2020ISCASPosition-Based CMOS Charge Qubits for Scalable Quantum Processors at 4K.Robert Bogdan Staszewski, Panagiotis Giounanlis, Ali Esmailiyan, Hongying Wang, Imran Bashir, Cagri Cetintepe, Dennis Andrade-Miceli, Mike Asker, Dirk Leipold, Teerachot Siriburanon, Andrii Sokolov, Elena Blokhina
2017ASPDACAn HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation.Dongsheng Yang, Wei Deng, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa
2016ASPDACAn automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection.Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa
2015ASPDACA 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection.Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa
2015ASPDACAn HDL-synthesized gated-edge-injection PLL with a current output DAC.Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa
2014ASPDACA dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation.Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2014ASPDACA swing-enhanced current-reuse class-C VCO with dynamic bias control circuits.Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa
2013ASPDACA sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers.Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa