Tetsuo Endoh
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
9
Venues
3
Active years
2001–2016
Best venue rank
C
Where they publish
Papers
9 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2016 | ISCAS | Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design. | Masanori Natsui, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu |
| 2015 | ISCAS | Nonvolatile logic and memory devices based on spintronics. | Tetsuo Endoh |
| 2014 | ISCAS | A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. | Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi |
| 2013 | ISCAS | An MTJ-based nonvolatile associative memory architecture with intelligent power-saving scheme for high-speed low-power recognition applications. | Yitao Ma, Tadashi Shibata, Tetsuo Endoh |
| 2012 | ASPDAC | Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme. | Shoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu |
| 2012 | ISCAS | High-speed simulator including accurate MTJ models for spintronics integrated circuit design. | Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh |
| 2010 | ISCAS | A compact and low power logic design for multi-pillar vertical MOSFETs. | Koji Sakui, Tetsuo Endoh |
| 2009 | DATE | MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. | Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu |
| 2001 | ASPDAC | An on-chip 96.5% current efficiency CMOS linear regulator. | Kazuhisa Sunaga, Tetsuo Endoh, Hiroshi Sakuraba, Fujio Masuoka |