| 2019 | SERA | Extracting Inclusion Graphs of API Member Sets to Improve Searchability. | Yushi Kondoh, Masashi Nishimoto, Keiji Nishiyama, Hideyuki Kawabata, Tetsuo Hironaka |
| 2019 | SERA | Supporting Program Understanding by Automatic Indexing of Functionalities in Source Code. | Masashi Nishimoto, Keiji Nishiyama, Hideyuki Kawabata, Tetsuo Hironaka |
| 2018 | APLAS | Traf: A Graphical Proof Tree Viewer Cooperating with Coq Through Proof General. | Hideyuki Kawabata, Yuta Tanaka, Mai Kimura, Tetsuo Hironaka |
| 2008 | FPL | Exploring compact design on high throughput coarse grained reconfigurable architectures. | Kazuya Tanigawa, Tetsuya Zuyama, Takuro Uchida, Tetsuo Hironaka |
| 2005 | ISCAS | Design of superscalar processor with multi-bank register file. | Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jrgen Mattausch |
| 2004 | ASPDAC | Compact 12-port multi-bank register file test-chip in 0.35m CMOS for highly parallel processors. | Tetsuya Sueyoshi, Hiroshi Uchida, Hans Jrgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka |
| 2002 | FPL | A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model. | Kazuya Tanigawa, Tetsuo Hironaka, Akira Kojima, Noriyoshi Yoshida |
| 2000 | ASPDAC | Prototype microprocessor LSI with scheduling support hardware for operating system on multiprocessor system. | Naoki Nishimura, Takahiro Sasaki, Tetsuo Hironaka |
| 1993 | ICS | A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking. | Takashi Hashimoto, Kazuaki J. Murakami, Tetsuo Hironaka, Hiroto Yasuura |
| 1992 | ICS | Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture. | Tetsuo Hironaka, Takashi Hashimoto, Keizo Okazaki, Kazuaki J. Murakami, Shinji Tomita |