Tetsuo Tada
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
1996–2004
Best venue rank
A
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2004 | ASPDAC | Opportunities with the open architecture test system. | Tetsuo Tada |
| 2001 | ITC | Test cost reduction by at-speed BISR for embedded DRAMs. | Yoshihiro Nagura, Michael Mullins, Anthony Sauvageau, Yoshinoro Fujiwara, Katsuya Furue, Ryuji Ohmura, Tatsunori Komoike, Takenori Okitaka, Tetsushi Tanizaki, Katsumi Dosaka, Kazutami Arimoto, Yukiyoshi Koda, Tetsuo Tada |
| 1996 | ITC | A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM. | Narumi Sakashita, Fumihiro Okuda, Ken'ichi Shimomura, Hiroki Shimano, Mitsuhiro Hamada, Tetsuo Tada, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe |