| 2026 | ISCAS | A 267-mV input and 122-ns fall time, pre-charged cross-coupled pulse voltage doubler for low-voltage thermoelectric energy harvesting. | Jingbo Li, Naoki Kurisu, Daisuke Kanemoto, Tetsuya Hirose |
| 2025 | ASPDAC | Low quiescent current LDO with FBPEC to improve PSRR specific frequency band for wearable EEG recording devices. | Kenji Mii, Daisuke Kanemoto, Tetsuya Hirose |
| 2025 | ASPDAC | Ultra Low-power Capacitively-coupled Chopper Amplifier Focusing on the Sparsity of Compressed Sensing for EEG Recording. | Kenji Mii, Daisuke Kanemoto, Tetsuya Hirose |
| 2025 | ISCAS | Development of Low-power and High-accuracy Wireless EEG Transmission System Using Compressed Sensing with an EEG Basis. | Daisuke Kanemoto, Eichi Takimoto, Tetsuya Hirose |
| 2025 | ISCAS | Low-power and Low-noise Amplifier with Intermittent Operation for Compressed Sensing in EEG Measurement Systems. | Kenji Mii, Daisuke Kanemoto, Tetsuya Hirose |
| 2025 | ISCAS | Sub-50-mV Static Flip-Flop Consisting of Recursive Stacking Body-Bias Logic Gates for Extremely Low-Voltage VLSIs. | Shintaro Sumi, Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose |
| 2024 | ISCAS | Reducing Power Consumption in LNA by Utilizing EEG Signals as Basis Matrix in Compressed Sensing. | Riku Matsubara, Daisuke Kanemoto, Tetsuya Hirose |
| 2023 | ISCAS | A Programmable Differential Bandgap Reference for Ultra-Low-Power IoT Edge Node Devices. | Yoshinori Itotagawa, Koma Atsumi, Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose |
| 2023 | ISCAS | EEG Measurements with Compressed Sensing Utilizing EEG Signals as the Basis Matrix. | Daisuke Kanemoto, Tetsuya Hirose |
| 2023 | ISCAS | Random Undersampling Wireless EEG Measurement Device using a Small TEG. | Takuya Miyata, Daisuke Kanemoto, Tetsuya Hirose |
| 2022 | ISCAS | Sub-50-mV Charge Pump and its Driver for Extremely Low-Voltage Thermal Energy Harvesting. | Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose |
| 2018 | ISCAS | Analytical Study of Multi-stage Switched-Capacitor Voltage Boost Converter for Ultra-low Voltage Energy Harvesting. | Yuichiro Nakazawa, Tetsuya Hirose, Toshihiro Ozaki, Yuto Tsuji, Shuto Kanzaki, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa |
| 2017 | ASPDAC | Sub-1-μs start-up time, 32-MHz relaxation oscillator for low-power intermittent VLSI systems. | Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa |
| 2017 | ISCAS | An area-efficient, 0.022-mm2, fully integrated resistor-less relaxation oscillator for ultra-low power real-time clock applications. | Hiroki Asano, Tetsuya Hirose, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa |
| 2017 | ISCAS | Near-field dual-use antenna for magnetic-field based communication and electrical-field based distance sensing in mm3-class sensor node. | Ryo Shirai, Jin Kono, Tetsuya Hirose, Masanori Hashimoto |
| 2015 | ASPDAC | A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated 3-terminal voltage converter with MPPT for low-voltage energy harvesters. | Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa |
| 2015 | ISCAS | A 0.19-V minimum input low energy level shifter for extremely low-voltage VLSIs. | Ryo Matsuzuka, Tetsuya Hirose, Yuzuru Shizuku, Nobutaka Kuroki, Masahiro Numa |
| 2011 | ASPDAC | A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder. | Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa |
| 2010 | ISCAS | Super-resolution technique for thermography with dual-camera system. | Shingo Chikamatsu, Tomohiro Nakaya, Masakazu Kouda, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa |
| 2009 | ASPDAC | A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. | Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya |
| 2009 | ISCAS | On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs. | Yusuke Tsugita, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya, Tetsuya Hirose |
| 2007 | ICONIP | Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning. | Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya |
| 2007 | IJCNN | Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning. | Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya |
| 2007 | ISCAS | Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs. | Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya |
| 2005 | IJCNN | Analog current-mode CMOS implementation of central pattern generator for robot locomotion. | Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya |
| 2004 | IJCNN | A MOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection. | Tetsuya Asai, Yusuke Kanazawa, Tetsuya Hirose, Yoshihito Amemiya |
| 2000 | HPCA | A DSM Architecture for a Parallel Computer Cenju-4. | Takeo Hosomi, Yasushi Kanoh, Masaaki Nakamura, Tetsuya Hirose |