| 2025 | FPL | FINN-GL: Generalized Mixed-Precision Extensions for FPGA-Accelerated LSTMS. | Shashwat Khandelwal, Jakoba Petri-Koenig, Thomas B. Preuer, Michaela Blott, Shanker Shreejith |
| 2024 | FPL | Shedding the Bits: Pushing the Boundaries of Quantization with Minifloats on FPGAs. | Shivam Aggarwal, Hans Jakob Damsgaard, Alessandro Pappalardo, Giuseppe Franco, Thomas B. Preuer, Michaela Blott, Tulika Mitra |
| 2020 | FPL | HyperLogLog Sketch Acceleration on FPGA. | Amit Kulkarni, Monica Chiosa, Thomas B. Preuer, Kaan Kara, David Sidler, Gustavo Alonso |
| 2020 | FPL | Using DSP Slices as Content-Addressable Update Queues. | Thomas B. Preuer, Monica Chiosa, Alexander Weiss, Gustavo Alonso |
| 2018 | DATE | Inference of quantized neural networks on heterogeneous all-programmable devices. | Thomas B. Preuer, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott |
| 2017 | DDECS | Implementation of an asynchronous bundled-data router for a GALS NoC in the context of a VSoC. | Patrick Russell, Jens Dge, Christoph Hoppe, Thomas B. Preuer, Peter Reichel, Peter Schneider |
| 2017 | FPL | Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs. | Thomas B. Preuer |
| 2017 | ICCD | Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic. | Michaela Blott, Thomas B. Preuer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser |
| 2015 | FPL | An LZ77-style bit-level compression for trace data compaction. | Kai-Uwe Irrgang, Thomas B. Preuer |
| 2015 | GI | Kompression von Tracedaten auf Bitebene basierend auf einem LZ77-Wrterbuchansatz. | Kai-Uwe Irrgang, Thomas B. Preuer, Rainer G. Spallek |
| 2014 | FPL | Ready PCIe data streaming solutions for FPGAs. | Thomas B. Preuer, Rainer G. Spallek |
| 2013 | FPL | Weasel: A platform-independent streaming-optimized SATA controller. | Patrick Lehmann, Thomas Frank, Oliver Knodel, Steffen Khler, Thomas B. Preuer, Rainer G. Spallek |
| 2012 | FCCM | Short-Read Mapping by a Systolic Custom FPGA Computation. | Thomas B. Preuer, Oliver Knodel, Rainer G. Spallek |
| 2011 | ARITH | Accelerating Computations on FPGA Carry Chains by Operand Compaction. | Thomas B. Preuer, Martin Zabel, Rainer G. Spallek |
| 2011 | FPL | FPGA-Specific Arithmetic Optimizations of Short-Latency Adders. | Hong Diep Nguyen, Bogdan Pasca, Thomas B. Preuer |
| 2010 | FPL | Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains. | Thomas B. Preuer, Rainer G. Spallek |
| 2009 | FPL | Mapping basic prefix computations to fast carry-chain structures. | Thomas B. Preuer, Rainer G. Spallek |
| 2007 | DSD | Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture. | Martin Zabel, Thomas B. Preuer, Peter Reichel, Rainer G. Spallek |