Thomas J. Snethen
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
2
Active years
1970–2014
Best venue rank
A*
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2014 | ITC | Efficient testing of hierarchical core-based SOCs. | Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen |
| 2010 | ITC | Low cost at-speed testing using On-Product Clock Generation compatible with test compression. | Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise |
| 2007 | ITC | Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation. | Anis Uzzaman, Bibo Li, Thomas J. Snethen, Brion L. Keller, Gary Grise |
| 1998 | ITC | Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip. | Mary P. Kusko, Bryan J. Robbins, Thomas J. Snethen, Peilin Song, Thomas G. Foote, William V. Huott |
| 1994 | ITC | Design of an Efficient Weighted-Random-Pattern Generation System. | Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams |
| 1977 | DAC | Simulator-oriented fault test generator. | Thomas J. Snethen |
| 1970 | DAC | Minimizing the problem of logic testing by the interaction of a design group with user-oriented facilities. | Manuel Correia, Donald Cossman, Franco Putzolu, Thomas J. Snethen |