Thomas Luinaud
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
4
Active years
2017–2022
Best venue rank
A
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2022 | ISCAS | An FPGA-based HW/SW Co-Verification Environment for Programmable Network Devices. | Mengyue Su, Jean-Pierre David, Yvon Savaria, Bill Pontikakis, Thomas Luinaud |
| 2021 | FPGA | Design Principles for Packet Deparsers on FPGAs. | Thomas Luinaud, Jeferson Santiago da Silva, J. M. Pierre Langlois, Yvon Savaria |
| 2020 | FPGA | Unleashing the Power of FPGAs as Programmable Switches. | Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois |
| 2020 | HPSR | Bridging the Gap: FPGAs as Programmable Switches. | Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois |
| 2018 | ICNP | One for All, All for One: A Heterogeneous Data Plane for Flexible P4 Processing. | Jeferson Santiago da Silva, Thibaut Stimpfling, Thomas Luinaud, Bachir Fradj, Bochra Boughzala |
| 2017 | FPGA | An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only). | Thomas Luinaud, Yvon Savaria, J. M. Pierre Langlois |