| 2023 | EDUCON | Automated Evaluation System for Microcontroller Assignments. | Fabian Steiner, Bernhard Lueger, Bernhard Wallisch, Thomas Polzer |
| 2018 | DDECS | Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA. | Florian Huemer, Thomas Polzer, Andreas Steininger |
| 2017 | DDECS | Measuring metastability using a time-to-digital converter. | Thomas Polzer, Florian Huemer, Andreas Steininger |
| 2016 | DDECS | A general approach for comparing metastable behavior of digital CMOS gates. | Thomas Polzer, Andreas Steininger |
| 2015 | DDECS | Containment of Metastable Voltages in FPGAs. | Robert Najvirt, Thomas Polzer, Florian Beck, Andreas Steininger |
| 2015 | DSD | Measuring the Distribution of Metastable Upsets over Time. | Thomas Polzer, Andreas Steininger |
| 2015 | DSD | Enhanced Metastability Characterization Based on AC Analysis. | Thomas Polzer, Andreas Steininger |
| 2013 | DSD | Digital Late-Transition Metastability Simulation Model. | Thomas Polzer, Andreas Steininger |
| 2012 | DSD | Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. | Varadan Savulimedu Veeravalli, Thomas Polzer, Andreas Steininger, Ulrich Schmid |
| 2009 | SSS | A Metastability-Free Multi-synchronous Communication Scheme for SoCs. | Thomas Polzer, Thomas Handl, Andreas Steininger |