| 2025 | DATE | Using OFF-set only for Corrupting Circuit to Resist Structural Attack in CAC Locking. | Hsiang-Chun Cheng, RuiJie Wang, TingTing Hwang |
| 2024 | DATE | A Hybrid Approach to Reverse Engineering on Combinational Circuits. | Wuqian Tang, Yi-Ting Li, Kai-Po Hsu, Kuan-Ling Chou, You-Cheng Lin, Chia-Feng Chien, Tzu-Li Hsu, Yung-Chih Chen, Ting-Chi Wang, Shih-Chieh Chang, TingTing Hwang, Chun-Yao Wang |
| 2023 | DATE | Expanding In-Cone Obfuscated Tree for Anti SAT Attack. | RuiJie Wang, Li-Nung Hsu, Yung-Chih Chen, TingTing Hwang |
| 2021 | ASPDAC | A Dynamic Link-latency Aware Cache Replacement Policy (DLRP). | Yen-Hao Chen, Allen C.-H. Wu, TingTing Hwang |
| 2017 | ASPDAC | Communication driven remapping of processing element (PE) in fault-tolerant NoC-based MPSoCs. | Chia-Ling Chen, Yen-Hao Chen, TingTing Hwang |
| 2017 | DATE | Architectural evaluations on TSV redundancy for reliability enhancement. | Yen-Hao Chen, Chien-Pang Chiu, Russell Barnes, TingTing Hwang |
| 2016 | DATE | A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements. | Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang |
| 2016 | DATE | Thermal-aware dynamic page allocation policy by future access patterns for Hybrid Memory Cube (HMC). | Wei-Hen Lo, Kai-zen Liang, TingTing Hwang |
| 2015 | DATE | Architecture of ring-based redundant TSV for clustered faults. | Wei-Hen Lo, Kang Chi, TingTing Hwang |
| 2014 | ASPDAC | Fault-tolerant TSV by using scan-chain test TSV. | Fu-Wei Chen, Hui-Ling Ting, TingTing Hwang |
| 2014 | ICCAD | Compaction-free compressed cache for high performance multi-core system. | Po-Yang Hsu, Pei-Lan Lin, TingTing Hwang |
| 2013 | ASPDAC | Stacking signal TSV for thermal dissipation in global routing for 3D IC. | Po-Yang Hsu, Hsien-Te Chen, TingTing Hwang |
| 2013 | ETS | Utilizing circuit structure for scan chain diagnosis. | Wei-Hen Lo, Ang-Chih Hsieh, Chien-Ming Lan, Min-Hsien Lin, TingTing Hwang |
| 2013 | ICCAD | Thread-criticality aware dynamic cache reconfiguration in multi-core system. | Po-Yang Hsu, TingTing Hwang |
| 2012 | DAC | Clock tree synthesis with methodology of re-use in 3D IC. | Fu-Wei Chen, TingTing Hwang |
| 2011 | ASPDAC | A physical-location-aware fault redistribution for maximum IR-drop reduction. | Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang |
| 2011 | ASPDAC | Enhanced Heterogeneous Code Cache management scheme for Dynamic Binary Translation. | Ang-Chih Hsieh, Chun-Cheng Liu, TingTing Hwang |
| 2011 | DATE | A new architecture for power network in 3D IC. | Hsien-Te Chen, Hong-Long Lin, Zicheng Wang, TingTing Hwang |
| 2011 | ICPP | Memory Mapping and Task Scheduling Techniques for Computation Models of Image Processing on Many-Core Platforms. | Ang-Chih Hsieh, Yi-Ta Wu, Shau-Yin Tseng, TingTing Hwang |
| 2010 | DATE | TSV redundancy: Architecture and design issues in 3D IC. | Ang-Chih Hsieh, TingTing Hwang, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li |
| 2009 | ASPDAC | Thermal-aware post compilation for VLIW architectures. | Wen-Wen Hsieh, TingTing Hwang |
| 2009 | DAC | New spare cell design for IR drop minimization in Engineering Change Order. | Hsien-Te Chen, Chieh-Chun Chang, TingTing Hwang |
| 2009 | DATE | Thermal-aware memory mapping in 3D designs. | Ang-Chih Hsieh, TingTing Hwang |
| 2009 | DATE | A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test. | Wen-Wen Hsieh, I-Sheng Lin, TingTing Hwang |
| 2008 | ICCAD | Transition-aware decoupling-capacitor allocation in power noise reduction. | Po-Yuan Chen, Che-Yu Liu, TingTing Hwang |
| 2007 | ICCAD | Skew aware polarity assignment in clock tree. | Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang |
| 2006 | ASPDAC | Switching-activity driven gate sizing and Vth assignment for low power design. | Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang |
| 2006 | DATE | Crosstalk-aware domino logic synthesis. | Yi-Yu Liu, TingTing Hwang |
| 2006 | ISCAS | Performance-driven crosstalk elimination at post-compiler level. | Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu |
| 2005 | ASPDAC | Functionality directed clustering for low power MTCMOS design. | Tsuang-Wei Chang, TingTing Hwang, Sheng-Yu Hsu |
| 2005 | ASPDAC | Low-power techniques for network security processors. | Yi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiun Huang, TingTing Hwang, Sheng-Yu Hsu |
| 2005 | ISCAS | A power-driven multiplication instruction-set design method for ASIPs. | Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu |
| 2004 | ASPDAC | Low power design using dual threshold voltage. | Yen-Te Ho, TingTing Hwang |
| 2004 | DATE | Decomposition of Instruction Decoder for Low Power Design. | Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu |
| 2004 | DATE | Crosstalk Minimization in Logic Synthesis for PLA. | Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang |
| 2004 | ISCAS | Output-pattern directed decomposition for low power design. | Chi-Wei Hu, TingTing Hwang |
| 2003 | DATE | G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. | Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang |
| 2003 | DATE | Decomposition of Extended Finite State Machine for Low Power Design. | MingHung Lee, TingTing Hwang, Shi-Yu Huang |
| 2003 | DATE | A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. | Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang |
| 2002 | ISCAS | Instruction buffering for nested loops in low power design. | Chi Ta Wu, TingTing Hwang |
| 2001 | ASPDAC | A construction of minimal delay Steiner tree using two-pole delay model. | LiYi Lin, Yi-Yu Liu, TingTing Hwang |
| 2001 | DATE | Binary decision diagram with minimum expected path length. | Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu |
| 1999 | ASPDAC | A Clustering Based Linear Ordering Algorithm for K-Way Spectral Partitioning. | Shiuann-Shiuh Lin, Wen-Hsin Chen, Wen-Wei Lin, TingTing Hwang |
| 1999 | DATE | Logic Transformation for Low Power Synthesis. | Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu |
| 1998 | DAC | A Re-engineering Approach to Low Power FPGA Design Using SPFD. | Jan-Min Hwang, Feng-Yi Chiang, TingTing Hwang |
| 1998 | ICCAD | Architecture driven circuit partitioning. | Chau-Shen Chen, TingTing Hwang, C. L. Liu |
| 1997 | DAC | Low Power FPGA Design - A Re-engineering Approach. | Chau-Shen Chen, TingTing Hwang, C. L. Liu |
| 1996 | DAC | Layout Driven Selecting and Chaining of Partial Scan. | Chau-Shen Chen, Kuang-Hui Lin, TingTing Hwang |
| 1995 | ASPDAC | Power recduction by gate sizing with path-oriented slack calculation. | How-Rern Lin, TingTing Hwang |
| 1995 | DAC | Boolean Matching for Incompletely Specified Functions. | Kuo-Hua Wang, TingTing Hwang |
| 1994 | ICCAD | Dynamical identification of critical paths for iterative gate sizing. | How-Rern Lin, TingTing Hwang |
| 1994 | ICCD | State Assignment for Power and Area Minimization. | Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin |
| 1993 | ICCAD | Combining technology mapping and placement for delay-optimization in FPGA designs. | Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin |
| 1990 | ICCD | Logic synthesis for programmable logic devices. | TingTing Hwang, Robert Michael Owens, Mary Jane Irwin |
| 1989 | DAC | Multi-Level Logic Synthesis Using Communication Complexity. | TingTing Hwang, Robert Michael Owens, Mary Jane Irwin |