| 2014 | DDECS | Designing of Test Pattern Generators for stimulation of crosstalk faults in bus-type connections. | Tomasz Garbolino |
| 2011 | CEC | Optimal on-line built-in self-test structure for system-reliability improvement. | Gregor Papa, Tomasz Garbolino |
| 2010 | DDECS | How to reduce size of a signature-based diagnostic dictionary used for testing of connections. | Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka |
| 2009 | DDECS | Effective BIST for crosstalk faults in interconnects. | Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka |
| 2008 | DDECS | Interconnect Faults Identification and Localization Using Modified Ring LFSRs. | Andrzej Hlawiczka, Krzysztof Gucwa, Tomasz Garbolino, Michal Kopec |
| 2007 | DDECS | Avoiding Crosstalk Influence on Interconnect Delay Fault Testing. | Tomasz Garbolino, Krzysztof Gucwa, Michal Kopec, Andrzej Hlawiczka |
| 2006 | DDECS | Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor. | Tomasz Garbolino, Michal Kopec, Krzysztof Gucwa, Andrzej Hlawiczka |
| 2006 | ETS | Test-per-Clock Detection, Localization and Identification of Interconnect Faults. | Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka |
| 2000 | ETS | Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path. | Tomasz Garbolino, Andrzej Hlawiczka, Adam Kristof |
| 1999 | EDCC | A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits. | Tomasz Garbolino, Andrzej Hlawiczka |