Tonmoy Dhar
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
2020–2022
Best venue rank
A
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2022 | DATE | A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement. | Tonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven M. Burns, Ramesh Harjani, Sachin S. Sapatnekar |
| 2021 | ASPDAC | Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. | Tonmoy Dhar, Jitesh Poojary, Yaguang Li, Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Susmita Dey Manasi, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar |
| 2020 | DATE | GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. | Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar |
| 2020 | ICCAD | The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). | Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar |
| 2020 | ICCAD | A general approach for identifying hierarchical symmetry constraints for analog circuit layout. | Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar |