Toru Sano
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
3
Active years
2008–2014
Best venue rank
B
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2014 | ASPDAC | An evaluation of an energy efficient many-core SoC with parallelized face detection. | Hiroyuki Usui, Jun Tanabe, Toru Sano, Hui Xu, Takashi Miyamori |
| 2013 | DATE | A near-future prediction method for low power consumption on a many-core processor. | Takeshi Kodaka, Akira Takeda, Shunsuke Sasaki, Akira Yokosawa, Toshiki Kizu, Takahiro Tokuyoshi, Hui Xu, Toru Sano, Hiroyuki Usui, Jun Tanabe, Takashi Miyamori, Nobu Matsumoto |
| 2013 | DATE | Development of low power many-core SoC for multimedia applications. | Takashi Miyamori, Hui Xu, Takeshi Kodaka, Hiroyuki Usui, Toru Sano, Jun Tanabe |
| 2010 | ASPDAC | MuCCRA-3: a low power dynamically reconfigurable processor array. | Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano |
| 2009 | FPL | MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. | Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano |
| 2009 | FPL | Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors. | Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano |
| 2008 | FPL | Instruction buffer mode for multi-context Dynamically Reconfigurable Processors. | Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano |