Travis N. Blalock
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
2005–2026
Best venue rank
A*
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ISCAS | A 97.63 fJ/conv-step 3 GSa/s 2-Way Time-Interleaved (TI) 3-Bit Flash ADC for Analog In-Memory Computing (IMC) Deep Learning (DL) Accelerators in 28-nm CMOS. | Jinhua Wang, Adam H. Slater, Travis N. Blalock, Steven M. Bowers |
| 2010 | DAC | SRAM-based NBTI/PBTI sensor system design. | Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, Mircea R. Stan |
| 2009 | ISCAS | Sub-threshold Operation and Cross-hierarchy Design for Ultra Low Power Wearable Sensors. | Benton H. Calhoun, Jonathan F. Bolus, Sudhanshu Khanna, Andrew D. Jurik, Alfred C. Weaver, Travis N. Blalock |
| 2009 | ISLPED | A 2.6 W sub-threshold mixed-signal ECG SoC. | Steven C. Jocke, Jonathan F. Bolus, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun |
| 2005 | ISCAS | A three-level toggle-avoid bus signaling scheme. | Yan Zhang, Travis N. Blalock, Mircea R. Stan |