A 97.63 fJ/conv-step 3 GSa/s 2-Way Time-Interleaved (TI) 3-Bit Flash ADC for Analog In-Memory Computing (IMC) Deep Learning (DL) Accelerators in 28-nm CMOS.

Jinhua Wang, Adam H. Slater, Travis N. Blalock, Steven M. Bowers

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