| 2014 | ICASSP | Design and implementation of a low power spike detection processor for 128-channel spike sorting microsystem. | Tsung-Chuan Ma, Tung-Chien Chen, Liang-Gee Chen |
| 2013 | ISCAS | Low-power multi-processor system architecture design for universal biomedical signal processing. | Li-Fang Cheng, Tung-Chien Chen, Liang-Gee Chen |
| 2012 | ISCAS | Exploration of reusing the pre-recorded training data set to improve the supervised classifier for EEG-based motor-imagery brain computer interfaces. | Yun-Yu Chen, Tung-Chien Chen, Chien-Chung Chen, Hsin-I Liao, Luk-Ting Sio, Liang-Gee Chen |
| 2011 | ICASSP | Power estimation scheme for lowpower oriented biomedical SoC extended to very deep submicron technology. | Hong-Hui Chen, Tung-Chien Chen, Cheng-Yi Chiang, Liang-Gee Chen |
| 2011 | ICASSP | Design and implementation of cubic spline interpolation for spike sorting microsystems. | Tung-Chien Chen, Yun-Yu Chen, Tsung-Chuan Ma, Liang-Gee Chen |
| 2010 | ISCAS | Accuracy and power tradeoff in spike sorting microsystems with cubic spline interpolation. | Yun-Yu Chen, Tung-Chien Chen, Liang-Gee Chen |
| 2010 | ISCAS | Sub-microwatt correlation integral processor for implantable closed-loop epileptic neuromodulator. | Yu-Hsin Chen, Tung-Chien Chen, Tsung-Hsueh Lee, Liang-Gee Chen |
| 2009 | ISCAS | Closed-loop Eyelid Reanimation System with Real-time Blink Detection and Electrochemical Stimulation for Facial Nerve Paralysis. | Kuanfu Chen, Tung-Chien Chen, Kimberly Cockerham, Wentai Liu |
| 2009 | ISCAS | On-chip Principal Component Analysis with a Mean Pre-estimation Method for Spike Sorting. | Tung-Chien Chen, Kuanfu Chen, Wentai Liu, Liang-Gee Chen |
| 2009 | ISCAS | 128-channel Spike Sorting Processor with a Parallel-folding Structure in 90nm Process. | Tung-Chien Chen, Wentai Liu, Liang-Gee Chen |
| 2007 | ICASSP | Low Power Cache Algorithm and Architecture Design for Fast Motion Estimation in H.264/AVC Encoder System. | Chuan-Yuan Tsai, Chen-Han Chung, Yu-Han Chen, Tung-Chien Chen, Liang-Gee Chen |
| 2007 | ISCAS | System Bandwidth Analysis of Multiview Video Coding with Precedence Constraint. | Pei-Kuei Tsung, Li-Fu Ding, Wei-Yin Chen, Shao-Yi Chien, Tung-Chien Chen, Liang-Gee Chen |
| 2006 | ASPDAC | Hardware architecture design of an H.264/AVC video codec. | Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen |
| 2006 | ICASSP | Architecture Design of Low Power Integer Motion Estimation for H. 264/AVC. | Tung-Chien Chen, Yu-Han Chen, Sung-Fang Tsai, Liang-Gee Chen |
| 2006 | ISCAS | Low power and power aware fractional motion estimation of H.264/AVC for mobile applications. | Tung-Chien Chen, Yu-Han Chen, Chuan-Yung Tsai, Liang-Gee Chen |
| 2005 | ISCAS | Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos. | To-Wei Chen, Yu-Wen Huang, Tung-Chien Chen, Yu-Han Chen, Chuan-Yung Tsai, Liang-Gee Chen |
| 2005 | ISCAS | Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC. | Tung-Chien Chen, Yu-Wen Huang, Chuan-Yung Tsai, Chao-Tsung Huang, Liang-Gee Chen |
| 2004 | ICASSP | Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC. | Tung-Chien Chen, Yu-Wen Huang, Liang-Gee Chen |
| 2004 | ISCAS | Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture. | Tung-Chien Chen, Yu-Wen Huang, Liang-Gee Chen |
| 2004 | ISCAS | Hardware architecture design for H.264/AVC intra frame coder. | Yu-Wen Huang, Bing-Yu Hsieh, Tung-Chien Chen, Liang-Gee Chen |
| 2003 | ISCAS | Computationally controllable integer, half, and quarter-pel motion estimator for MPEG-4 Advanced Simple Profile. | Wei-Min Chao, Tung-Chien Chen, Yung-Chi Chang, Chih-Wei Hsu, Liang-Gee Chen |