| 2024 | SOSP | SilvanForge: A Schedule-Guided Retargetable Compiler for Decision Tree Inference. | Ashwin Prasad, Sampath Rajendra, Kaushik Rajan, R. Govindarajan, Uday Bondhugula |
| 2023 | ASPLOS | HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description. | Kingshuk Majumder, Uday Bondhugula |
| 2022 | CC | MLIR-based code generation for GPU tensor cores. | Navdeep Katel, Vivek Khandelwal, Uday Bondhugula |
| 2022 | MICRO | Treebeard: An Optimizing Compiler for Decision Tree Based ML Inference. | Ashwin Prasad, Sampath Rajendra, Kaushik Rajan, R. Govindarajan, Uday Bondhugula |
| 2021 | CGO | MLIR: Scaling Compiler Infrastructure for Domain Specific Computation. | Chris Lattner, Mehdi Amini, Uday Bondhugula, Albert Cohen, Andy Davis, Jacques A. Pienaar, River Riddle, Tatiana Shpeisman, Nicolas Vasilache, Oleksandr Zinenko |
| 2021 | ICS | A practical tile size selection model for affine loop nests. | Kumudha Narasimhan, Aravind Acharya, Abhinav Baid, Uday Bondhugula |
| 2020 | CC | Bitwidth customization in image processing pipelines using interval analysis and SMT solvers. | Suresh Purini, Vinamra Benara, Ziaul Choudhury, Uday Bondhugula |
| 2019 | ICS | Optimizing the linear fascicle evaluation algorithm for many-core systems. | Karan Aggarwal, Uday Bondhugula |
| 2018 | PLDI | Polyhedral auto-transformation with no integer linear programming. | Aravind Acharya, Uday Bondhugula, Albert Cohen |
| 2018 | PPoPP | An effective fusion and tile size model for optimizing image processing pipelines. | Abhinav Jangda, Uday Bondhugula |
| 2017 | SC | Optimizing geometric multigrid method computation using a DSL approach. | Vinay Vasista, Kumudha Narasimhan, Siddharth Bhat, Uday Bondhugula |
| 2016 | POPL | SMO: an integrated approach to intra-array and inter-array storage optimization. | Somashekaracharya G. Bhaskaracharya, Uday Bondhugula, Albert Cohen |
| 2015 | ASPLOS | PolyMage: Automatic Optimization for Image Processing Pipelines. | Ravi Teja Mullapudi, Vinay Vasista, Uday Bondhugula |
| 2015 | PPoPP | PLUTO+: near-complete modeling of affine transformations for parallelism and locality. | Aravind Acharya, Uday Bondhugula |
| 2014 | ICS | Effective automatic computation placement and dataallocation for parallelization of regular programs. | Chandan Reddy, Uday Bondhugula |
| 2013 | CC | PolyGLoT: A Polyhedral Loop Transformation Framework for a Graphical Dataflow Language. | Somashekaracharya G. Bhaskaracharya, Uday Bondhugula |
| 2013 | SC | Compiling affine loop nests for distributed-memory parallel architectures. | Uday Bondhugula |
| 2012 | SC | Tiling stencil computations to maximize parallelism. | Vinayaka Bandishti, Irshad Pananilath, Uday Bondhugula |
| 2011 | POPL | Loop transformations: convexity, pruning and optimization. | Louis-Nol Pouchet, Uday Bondhugula, Cdric Bastoul, Albert Cohen, J. Ramanujam, P. Sadayappan, Nicolas Vasilache |
| 2010 | SC | Combined Iterative and Model-driven Optimization in an Automatic Parallelization Framework. | Louis-Nol Pouchet, Uday Bondhugula, Cdric Bastoul, Albert Cohen, J. Ramanujam, P. Sadayappan |
| 2009 | PPoPP | Compiler-assisted dynamic scheduling for effective parallelization of loop nests on multicore processors. | Muthu Manikandan Baskaran, Nagavijayalakshmi Vydyanathan, Uday Bondhugula, J. Ramanujam, Atanas Rountev, P. Sadayappan |
| 2009 | SC | Compact multi-dimensional kernel extraction for register tiling. | Lakshminarayanan Renganarayanan, Uday Bondhugula, Salem Derisavi, Alexandre E. Eichenberger, Kevin O'Brien |
| 2008 | CC | Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model. | Uday Bondhugula, Muthu Manikandan Baskaran, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan |
| 2008 | ICS | A compiler framework for optimization of affine loop nests for gpgpus. | Muthu Manikandan Baskaran, Uday Bondhugula, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan |
| 2008 | PLDI | A practical automatic polyhedral parallelizer and locality optimizer. | Uday Bondhugula, Albert Hartono, J. Ramanujam, P. Sadayappan |
| 2008 | PPoPP | Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories. | Muthu Manikandan Baskaran, Uday Bondhugula, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan |
| 2007 | PLDI | Effective automatic parallelization of stencil computations. | Sriram Krishnamoorthy, Muthu Manikandan Baskaran, Uday Bondhugula, J. Ramanujam, Atanas Rountev, P. Sadayappan |
| 2007 | PPoPP | Automatic mapping of nested loops to FPGAS. | Uday Bondhugula, J. Ramanujam, P. Sadayappan |
| 2006 | FCCM | Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths. | Uday Bondhugula, Ananth Devulapalli, James Dinan, Joseph Fernando, Pete Wyckoff, Eric Stahlberg, P. Sadayappan |
| 2005 | HiPC | High Performance RDMA Based All-to-All Broadcast for InfiniBand Clusters. | Sayantan Sur, Uday Bondhugula, Amith R. Mamidala, Hyun-Wook Jin, Dhabaleswar K. Panda |