| 2020 | ECCV | Thanks for Nothing: Predicting Zero-Valued Activations with Lightweight Convolutional Neural Networks. | Gil Shomron, Ron Banner, Moran Shkolnik, Uri C. Weiser |
| 2020 | MICRO | Non-Blocking Simultaneous Multithreading: Embracing the Resiliency of Deep Neural Networks. | Gil Shomron, Uri C. Weiser |
| 2015 | ISCA | Semantic locality and context-based prefetching using reinforcement learning. | Leeor Peled, Shie Mannor, Uri C. Weiser, Yoav Etsion |
| 2014 | MICRO | Loop-Aware Memory Prefetching Using Code Block Working Sets. | Adi Fuchs, Shie Mannor, Uri C. Weiser, Yoav Etsion |
| 2011 | ICCD | Memristor-based IMPLY logic design procedure. | Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman |
| 2010 | ICCD | Threads vs. caches: Modeling the behavior of parallel workloads. | Zvika Guz, Oved Itzhak, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser |
| 2009 | MICRO | Multiple clock and voltage domains for chip multi processors. | Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser |
| 2008 | SPAA | Utilizing shared data in chip multiprocessors with the nahalal architecture. | Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser |
| 1999 | ISCA | Correlated Load-Address Predictors. | Michael Bekerman, Stphan Jourdan, Ronny Ronen, Gilad Kirshenboim, Lihu Rappoport, Adi Yoaz, Uri C. Weiser |
| 1991 | ICPP | Efficient Systolic Array for Matrix Multiplication. | Fabian Klass, Uri C. Weiser |