| 2017 | DSD | Setup for an Experimental Study of Radiation Effects in 65nm CMOS. | Bernhard Fritz, Andreas Steininger, Vclav Simek, Varadan Savulimedu Veeravalli |
| 2016 | DSD | Design and Physical Implementation of a Target ASIC for SET Experiments. | Varadan Savulimedu Veeravalli, Andreas Steininger |
| 2016 | ETS | Study of a delayed single-event effect in the Muller C-element. | Varadan Savulimedu Veeravalli, Andreas Steininger |
| 2015 | DSD | Reliable and Continuous Measurement of SET Pulse Widths. | Varadan Savulimedu Veeravalli, Andreas Steininger |
| 2014 | ICCD | Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. | Andreas Steininger, Varadan Savulimedu Veeravalli, Dan Alexandrescu, Enrico Costenaro, Lorena Anghel |
| 2012 | DDECS | Radiation-tolerant combinational gates - an implementation based comparison. | Varadan Savulimedu Veeravalli, Andreas Steininger |
| 2012 | DSD | Protecting an Asynchronous NoC against Transient Channel Faults. | Syed Rameez Naqvi, Varadan Savulimedu Veeravalli, Andreas Steininger |
| 2012 | DSD | Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. | Varadan Savulimedu Veeravalli, Thomas Polzer, Andreas Steininger, Ulrich Schmid |