Vasantha M. H.
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
2
Active years
2021–2026
Best venue rank
National
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | VLSID | A Robust CMOS Schmitt Trigger Architecture with Improved Noise Immunity and Hysteresis Control. | Siddharth R. K., Shasidhar Reddy, Cheni Deepankar, Karteek Dokala, Vasantha M. H., Nithin Kumar Y. B. |
| 2026 | VLSID | Partial Product Grouping-Based Approximate Multipliers for Deep Learning Inference. | Boggu Priestly Samarpana, Siddharth R. K., Geeta Shet, Nithin Kumar Y. B., Vasantha M. H. |
| 2025 | ISCAS | A 0.9 V Configurable Dual Mode Comparator using a Supply Boosting Technique. | Sourabh Mestry, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Edoardo Bonizzoni |
| 2023 | VLSID | A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process. | Rupesh D. Kadhao, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Devesh Dwivedi |
| 2021 | ISCAS | A 1-V, 5-Bit, 180-W, Differential Pulse Position Modulation ADC in 65-nm CMOS Process. | Peta Guruprakashkumar, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Edoardo Bonizzoni |