Veeresh Babu Vulligaddala
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
2015–2017
Best venue rank
National
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2017 | ISCAS | CMOS mixed signal SoC for low-side current sensing. | Rahul Thottathil, Veeresh Babu Vulligaddala, Bibhudatta Sahoo |
| 2017 | VLSID | A Switched-Capacitor Amplifier with True Rail-to-Rail Input Range without Using a Rail-to-Rail Op-Amp. | Anjali Gopinath, Ravi Kumar Adusumalli, Veeresh Babu Vulligaddala, M. B. Srinivas |
| 2015 | VLSID | A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application. | T. Rahul, Bibhudatta Sahoo, S. Arya, S. J. Parvathy, Veeresh Babu Vulligaddala |