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Venelin Angelov

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

3

Venues

1

Active years

2008–2010

Best venue rank

B

Where they publish

Papers

3 indexed papers, newest first.

YearVenueTitleAuthors
2010FPLAn FPGA-based High-Speed, Low-Latency Processing System for High-Energy Physics.Stefan Kirsch, Felix Rettig, Dirk Hutter, Jan de Cuveland, Venelin Angelov, Volker Lindenstruth
2009FPLThe educational processor Sweet-16.Venelin Angelov, Volker Lindenstruth
2008FPLAn FPGA-based high-speed, low-latency trigger processor for high-energy physics.Jan de Cuveland, Felix Rettig, Venelin Angelov, Volker Lindenstruth